The present invention relates to a MOS transistor in which MOS transistor cells having different gate threshold voltages are connected in parallel and also relates to a switching power supply which uses the MOS transistor as a switching element.
AMOS transistor used as a switching element etc. for a switching power supply is formed by connecting a plurality of cells in parallel in order to lower an on-resistance value thereof. FIG. 7 schematically shows the structure of the section of the cell. That is, a reference numeral 81 depicts a gate electrode formed by poly-silicon, 82 an insulation layer for insulating the gate electrode 81, 84 an N+ region, and 83 a metal layer formed by aluminum silicon etc. The metal layer is coupled to the N+ region 84 and serves as a source electrode. A reference numeral 85 depicts a P− region, 86 an N− region, 87 a N+ region and 88 a metal plate serving as a drain electrode. When a voltage is applied to the gate electrode 81, a channel 89 with a depth corresponding to the applied voltage is formed and so a current flows from the drain to the source.
The gate voltage (hereinafter called a gate threshold voltage) when the channel is formed and a current starts to flow from the drain to the source changes in accordance with the change of the thickness of the gate electrode 81. That is, when the thickness of the gate electrode 81 is made smaller, the gate threshold voltage becomes lower. In contrast, when the thickness of the gate electrode 81 is made larger, the gate threshold voltage becomes higher. Thus, the thickness of the gate electrode 81 is determined such that the gate threshold voltage becomes a desired value. The thickness of the gate electrodes is formed to be entirely same on the same chip (first conventional technique).
A conventional technique proposed in the Unexamined Japanese Patent Application Publication No-2001-36388 discloses in the description from p. 19, line 20 to p. 20, line 16 such a configuration that, as to a plurality of MOS transistor cells formed on a single chip, the gate threshold voltages thereof are set to values suited to a required condition (second conventional technique).
A conventional technique proposed in the Unexamined Japanese Patent application Publication No. Hei 11-307650 discloses that, in an IC provided with a comparator, a mobility of a load side MOS transistor is made smaller than that of a differential side MOS transistor, and a mutual conductance gm of the load side MOS transistor is made smaller than that of the differential side MOS transistor. Thus, an offset voltage of the comparator using the MOS transistor can be reduced without increasing an occupied area (third conventional technique).
A conventional technique proposed in the Unexamined Japanese Patent Application Publication No. 2002-16238 discloses that an amplitude voltage of a column selection signal can be reduced by reducing the thickness of the gate oxide film of a MOS transistor which receives the column selection signal (fourth conventional technique).
FIG. 9 shows the configuration of another conventional technique of a switching power supply which uses a MOS transistor as a switching element and performs partial resonance. That is, in this technique, a switching pulse 72 outputted from a control circuit 71 is induced to the gate of a MOS transistor 74 through a saturable inductor L7. Thus, as shown in FIG. 10, although the switching pulse 72 rises abruptly, the gate voltage increases slowly as shown by a line 73. As a result, a current for discharging electric charges accumulated in a parasitic capacity component C7 is suppressed to a small value as shown by a steady line 78 (in this respect, a dotted line 79 represents change of a current for discharging the parasitic capacity component C7 in the case where the saturable inductor L7 is not provided. Therefore, the switching loss can be reduced (fifth conventional technique).
However, when the first conventional technique is used, there arises a following problem. That is, the MOS transistor formed by connecting a plurality of the cells in parallel has a large input capacity. Thus, when a pulse is applied to the gate, the gate voltage does not increase abruptly as shown by a reference numeral 98 in FIG. 8. As a result, it takes a ling time until the gate voltage exceeds a gate threshold voltage Vth8. Supposing that the increasing rate of the gate voltage is constant, the lower the gate threshold voltage is, the faster the timing when a current starts to flow into the MOS transistor becomes. However, since the MOS transistor with a low gate threshold voltage is thin in its gate and large in its area, the input capacity thereof is large. Thus, the MOS transistor with a low gate threshold voltage is lower in the increasing speed of the gate voltage as shown by a line 97 as compared with a MOS transistor with a high gate threshold voltage (shown by the line 98). Therefore, although the gate threshold voltage is set to a small value of Vth7, the timing when a current starts to flow into the MOS transistor becomes almost same as the case of the MOS transistor with a high gate threshold voltage. Thus, in the case of making earlier or faster the timing where the MOS transistor shifts in an ON state, it is required to enhance the driving ability of a driving circuit for driving the gate.
According to the second conventional technique, the MOS transistor cells formed so that the gate threshold voltages thereof are set to satisfy the required condition is arranged in a manner that each of these cells is used as a MOS transistor by itself. Thus, when considering the second conventional technique in a view point of solving the aforesaid problem, this second conventional technique is difficult to be applied.
Further, when considering the third and fourth conventional techniques in a view point of solving the aforesaid problem, these conventional techniques are also difficult to be applied.
When the fifth conventional technique is employed, although the switching loss can be reduced, the saturable inductor L7 is required for the reduction. On the other hand, saturable inductor L7 is expensive. That is, the fifth conventional technique causes a problem that the number of parts increases and costs of the parts also increase.